AN EFFICIENT GLITCH MITIGATION TECHNIQUE FOR LOW-POWER MULTIPLIER CIRCUITS

Abstract

A couple of significant methods for processing digital signals that involve multiplication are filtering and the fast Fourier transforms (FFT). A common tool for achieving lightning-fast processing speeds is the parallel array multiplier. The majority of a digital signal processor's power goes into its multipliers, therefore finding ways to make them more efficient is a key component of developing low-power DSP systems. Constructing a full adder (FA) with minimal power consumption is a straightforward solution. Alterations done to the building can potentially compromise its strength. If required, omit sections that do not contain any missing goods. Several multipliers are constructed from a low-power, complete adder that uses ten transistors, as described in this article. In order to evaluate various instruments, these criteria are utilized. A fine-grained MTCMOS cell can prevent power leakage by utilizing power gating.